Full flexibility

We develop and provide generators, windows and linux executables, that create the RTL design based on your configuration inputs. In essence, we implement your desired functionality, while you remain in control over capacities, bit widths, and various design-tradeoffs.

Your Benefits:

  • Fast iteration
  • Infinite configuration changes
  • No commitment to specific configuration
  • Full access to source
  • No site/product/node restriction

Vendor independence

Our generators produce regular, synthesizable vhdl 2008 output. Output using your choiceo of hardware description language is also possible. This output can be attuned to different target devices and synthesis tools, leaving you in control and with the option to switch devices or even device vendors in the future.

Your Benefits:

  • Regular vhdl 2008 output
  • With or without vendor macros
  • Attributes and sdc/xdc files can be attuned to common synthesis tools

Easy integration

Integration into your code base is facilitated by the generation of an instantiation template as well as an interface package of important constants and properties of the IP-core for use in generics of your code. Both are configuration specific and reflect the settings you chose when generating the IP-core.

Your Benefits:

  • Easy instantiation
  • Your code can adapt to parameters of the core

Extensive documentation

Alongside the generator, we provide extensive documentation detailing the use of the generator and its configuration options. A high level explanation of the implemented algorithm and discussion of the parameter tradeoffs enable your engineers to quickly configure the core for your specific requirements.

Dynamic interface documentation

The high flexibility of our RTL designs has a strong impact on the cores' behaviors. Yet, your engineers are never left guessing.

Our generators produce an Interface Documentation that details the specifics of the core as it was configured. Text, tables and schematics are populated with the actual attributes of the core, whether explicitly configured or inferred.

Time: N/A clock: N/A in_ready: N/A in_cmd_valid: N/A in_cmd_opcode: N/A 0xX 0x0 0x2 0x5 0x0 0xX in_cmd_connectionIndex: N/A 0xXXX 0x020 0xXXX in_cmd_sequenceNumber: N/A 0xXXXXXXXXXXXXXXXX in_cmd_windowSize: N/A 0xXXXXX in_frame_valid: N/A in_frame_channel: N/A 0xX in_frame_startofpacket: N/A in_frame_endofpacket: N/A in_frame_empty: N/A 0xX 0x0 0xX 0x0 0xX in_frame_error: N/A in_frame_data: N/A out_ready: N/A out_result_valid: N/A out_result_data: N/A 0xX 0x3 0xX 0x1 0x2 0xX out_frame_valid: N/A out_frame_channel: N/A 0xX out_frame_startofpacket: N/A out_frame_endofpacket: N/A out_frame_empty: N/A 0xX 0x0 0xX out_frame_error: N/A out_frame_data: N/A

Example waveforms for every configuration

The Interface Configuration even contains reference waveforms in interactive viewers for select demonstration test benches. The waveforms are created using an internal simulator, thus ensuring that they reflect exactly the configured behavior.

Well tested

Our RTL designs are well tested throughout their design hierarchy. Unit tests cover the smallest subcomponents, test benches and fuzzing-tests the larger IP-cores. In cases where we provide reference drivers for an IP-core, we perform closed loop simulations of the RTL design and the reference drivers.

Our IP-core level test benches and fuzzing tests are included in the generator. They can be executed with the internal simulator for each specific configuration, but can also be exported into vhdl test benches.


Get in touch! We are more than happy to discuss your project and how we can help.

Contact us and we will set up an online meeting with our engineers.

You can also download and check out one of our existing products which demonstrate these concepts.