Memory Interfaces
Section 3.1: Second Stage Memory
The properties that are expected of the external memory are listed in Table 3.2.
Field Name | Width | In/Out/Meta | Description |
---|---|---|---|
bitmap_rd_read | 1b | out | Asserted high to signal a read. When high, the memory content adddressed bybitmap_rd_address is expected on bitmap_rd_readdata after 5 cycles (subject to read-during-write conflicts). Similarly when low, the corresponding beat after 5 cycles in bitmap_rd_readdata may be undefined. |
bitmap_rd_address | 20b | out | Memory address to read from. Address is in words. |
bitmap_rd_readdata | 256b | in | Memory read from the address applied to bitmap_rd_address 5 cycles earlier (subject to read-during-write conflicts). |
bitmap_wr_write | 1b | out | Asserted high to signal a write. |
bitmap_wr_address | 20b | out | Memory address to write to. Address is in words. |
bitmap_wr_writedata | 256b | in | Data to write to the memory at the address bitmap_wr_address |
Table 3.1: Signals of the portmap of the core's top entity to which the external memory must be connected. In/out direction from the perspective of this core.
Parameter Name | Parameter Value |
---|---|
Total size | 256Mib |
Width (size of a word) | 256 |
Depth (number of words) | 1048576 |
Read latency (in cycles) | 5 |
Read during write policy (cross port) | DONT_CARE |
Table 3.2: Properties that are expected of the external memory.
The memory is expected to have a fixed read latency of 5 cycles. A change of read address should result in (potentially) different data being output 5 cycles later. If reads and writes happen to the same address but in different cycles, they are expected to be consistent chronologically, i.e. a later read picking up an earlier write. If a read and write happen to the same address in the same cycle, the write is expected to succeed, but the read may return undefined data.