Anti-Replay Core - IP Interface Description

Section 1.1: Introduction

This is the generated interface documentation of the Anti-Replay Core. For a detailed explanation of this core's functionality, its generation and what parameters are available, see the accompanying IP User Guide. This document only describes characteristics of the core specific to the chosen configuration such as registers, timings, etc. For reference, the chosen configuration options can be reviewed in Section 1.6.

Section 1.2: Table of Contents

Section 1.3: List of Tables

Section 1.4: List of Waveforms

Section 1.5: List of Figures

  • Anti-Replay Core - IP Interface Description: Anti-Replay Core - IP Interface Description
  • Interface Description: Interface Description
  • Memory Interfaces: Memory Interfaces
  • Clocks and Resets: Clocks and Resets
  • Example Waveforms: Example Waveforms

Section 1.6: Configuration Options

This section lists all configuration options that may have an influence on the generated core.
Parameter Name Parameter Value
Maximum number of connections 16384
Number of bits in sequence number 64
Virtual window size range 1 - 16777215 (inclusive)
Physical window size 16128 (highest seen sequence number is part of window)
Pipelining amount (core latency) 16 cycles
Minimum reset cycles Explicit reset disabled
Table 1.1: Selection of the most important configuration options and inferred parameters at a glance.
Parameter Name Parameter Value
Synthesis tool intel_quartus
Table 1.2: Chosen synthesis tool configuration
Parameter Name Parameter Value
Vendor intel
Family Arria 10
Device 10AX115N2F40I1SG
Has MLAB yes
Has M20K yes
Table 1.3: Chosen target technology configuration
Parameter Name Parameter Value
clock name clock
clock reset reset
frequency 220 MHz
trigger event RISING
reset type NONE
memory reset type NONE
reset active HIGH
initialize registers yes
initialize memory yes
Table 1.4: Chosen clock configuration
The following lists the configuration options of the core itself in yaml form. Missing values are filled in with the used defaults.
/:
  connection_addr_width: 14
  virtual_window_width: 24
  sequence_number_width: 64
  frame_stream:
    dataBitsPerSymbol: 8
    emptyWithinPacket: false
    errorDescriptor:
      []
    firstSymbolInHighOrderBits: true
    maxChannel: 0
    readyLatency: 0
    readyAllowance: 0
    channel_width: 1
    data_width: 512
    error_width: 1
    userdata_width: 0
/FrameAdapter0/AntiReplay0:
  window_addr_width: 14
  memory_word_width: 256
  pipelining: moderate
/FrameAdapter0/AntiReplay0/active0/scl_memory0:
  type: DONT_CARE
/FrameAdapter0/AntiReplay0/lastSequenceNumber0:
  step_compare_bit_limit: 32
/FrameAdapter0/AntiReplay0/lastSequenceNumber0/stage0/scl_memory0:
  type: DONT_CARE
  readLatency: 2
/FrameAdapter0/AntiReplay0/lastSequenceNumber0/stage1/scl_memory0:
  type: DONT_CARE
  readLatency: 2
/FrameAdapter0/AntiReplay0/FirstLookupStage0/scl_memory0:
  type: DONT_CARE
/FrameAdapter0/AntiReplay0/FirstLookupStage0/mux_large0:
  step_selector_bit_limit: 6
/FrameAdapter0/AntiReplay0/SecondLookupStage0/scl_memory0:
  type: EXTERNAL
  readLatency: 5
  prefix: bitmap
/FrameAdapter0/AntiReplay0/IsReplay0/mux_large0:
  step_selector_bit_limit: 6
/FrameAdapter0/FrameFifo0/scl_fifo0/scl_memory0:
  type: DONT_CARE
/FrameAdapter0/scl_fifo0/scl_memory0:
  type: DONT_CARE