An industry-proven, C++ based RTL design tool offering high flexibility and reusability.

We are the developers of Gatery, a C++ based Hardware Construction Library for building high density integrated logic circuits i.e. semiconductors or microchips. Gatery allows developping cutting edge RTL designs at a fraction of the normal development cost, while offering a high degree of configurability to our customers. It aspires to increase productivity and reuse.

Inspired by concepts and methods of the software development domain, it addresses many of the issues that the de-facto industry standard languages VHDL and Verilog suffer from.

Designs implemented in Gatery can be converted or exported to VHDL to seamlessly integrate with existing codebases, tools and workflows.

Best of all, Gatery is Open Source and free for personal and commercial use.

We believe that the time is ripe for more accessible digital circuit design, whether because increasing transistor according to Moore’s Law, increasing demand for communication according to Nielsen’s Law, or the urgent need to minimize energy use by information and comnmunication technology. Gatery is our effort to bring about this change.

See code on Github See tutorial


Strong Meta Programming Focus

Meta Programming is the concept of not directly writing a computer program, but rather writing an algorithm that, given some configuration, generates a computer program for that configuration. In the software domain, it allows to achieve a much better trade-off between code reusability and code performance. Similarly, in the domain of integrated logic circuits, it is essential to improving design reusability without sacrificing speed or area. In Gatery, like in all Hardware Construction Languages/Libraries, the meta programming ability comes from the host language. Since the logic circuit design arises from the execution of Gatery design, all control flow mechanisms can be used to affect the final logic design. What templates are to C++, the entire might of C++ is to Gatery. Any input or configuration file can be read, any computation be performed, to determine how the hardware design is to be built. The freedom to control the logic design creation programmatically is inherent to Gatery and its entire language stack of components. All benefits in terms of productivity and reusability propagate from the smallest component to the biggest IP-cores.

Mutable Variable Paradigm

All signals in Gatery follow the paradigm of mutable variables, as is common in programming languages. This reduces clutter constructing a signal through a sequence of instructions, such as composing a sum one summand at a time. But it also has a strong synergy with the meta programming aspect of Gatery as the behavior of a design can easily changed by modifying an existing variable.

outStream.valid = '1';

// We need input A
IF (!inStreamA.valid)
	outStream.valid = '0';

// We also need input B
IF (!inStreamB.valid)
	outStream.valid = '0';
UInt sum(const std::vector<UInt> &data) {
	UInt res = "10b0";
	for (const auto &v : data)
		res += v;
	return res;

Clean Syntax

The syntax of Gatery is much less verbose than in traditional HDLs. Reasonable defaults help prevent clutter and prevent mistakes. Clocks and resets are controlled via scopes alleviating the need to specify them for every register.

UInt histogram(UInt idx, Bit inc) {
	// All registers derive clock
	// from a global clock scope

	Memory<UInt> mem(32, 8_b);
	UInt bucket = mem[idx];

	// Automatic register retiming and
	// read modify write hazard detection
	IF (inc)
		mem[idx] = bucket + 1;

	// Register to make read synchronous
	bucket = reg(bucket);
	return bucket;

Full Control

Even though Gatery tries to facilitate logic circuit design with concepts and reasonable defaults that mimic in many places the mindsets of software developers, Gatery is not High-Level Synthesis. The designer retains full control over every aspect of the design, without having to wrestle with the complicated inference mechanisms of HLS. Whats more, oftentimes a first draft can be designed and then, where necessary, be refined and optimized, all without having to switch from HLS to HDL.

// Perform some iterations of the Binary GCD
// algorithm with some dirty bit tricks
for (size_t i = 0; i < iterationsPerClock; ++i) {
	IF (a != b) {
		const Bit a_odd = a.lsb();
		const Bit b_odd = b.lsb();

		IF (!a_odd) a >>= 1;
		IF (!b_odd) b >>= 1;

		IF (!a_odd & !b_odd) d += 1u;

		IF (a_odd & b_odd) {
			UInt abs = cat('0', a) - cat('0', b);
			a = mux(abs.msb(), {a,b});
			b = (abs(0, b.size()) ^ abs.msb()) >> 1;

Open License

Gatery is free software under the LGPL license. This allows anyone to freely use it, even for commercial closed source projects, as long as modifications to Gatery itself are published under LGPL. Contributions and feedback are very welcome.

See license

Industry Backed

Gatery is being developed and used by Synogate, a company specializing on highly flexible IP-core development. Synogate is committed to Gatery, by using it for commercial development their IP-cores but also by advancing the Gatery through steady improvements to the core library and standard components library.